Semiconductor devices often contain dielectric layers (e.g., a layer composed of silicon dioxide) grown or deposited on a semiconductor substrate (e.g., a silicon substrate). Semiconductor wafers, including dielectric layers, are used in manufacturing integrated circuits (IC's) serving as microprocessors, memories, etc. Modern IC's incorporate very large numbers (currently exceeding 109 elements per chip) of microelectronic devices such as metal-oxide-semiconductor (MOS) capacitors and MOS-field effect transistors (MOSFET). Their functioning depends on properties of dielectric layers. In IC fabrication, there is a need to precisely monitor the properties of dielectrics after dielectric growth or deposition and after other processing steps. Any deviation of dielectric properties from very strict specification can alter the performance of microelectronic devices and the manufacturing yield of integrated circuits. The key dielectric properties are dielectric capacitance and the corresponding electrical thickness, electrical leakage current across a dielectric, and electric charge in a dielectric layer and at an interface between the semiconductor and dielectric.
Non-contact charge-voltage metrology is an exemplary technique for monitoring all these properties of dielectrics disposed on a semiconductor wafer. Charge-voltage metrology includes depositing an ionic charge on the surface of a dielectric by means of corona discharge. Ionic charge induces a voltage drop across a dielectric and across the surface region of a semiconductor. By measuring these voltages with a vibrating capacitor method a charge-voltage data is obtained i.e. the Q-V data and the voltage time decay after charging.
Once the charge-voltage data is acquired, the parameters of a dielectric can be determined. For example, the dielectric capacitance CD is determined from ΔQ/ΔV measured in appropriate surface charge range. The dielectric leakage current is determined form the voltage time decay rate ΔV/Δt as discussed by Lagowski et al. in U.S. Pat. No. 6,597,193, which is herein incorporated by reference.
The interface trapped charge, Qit, is determined from a difference between the deposited corona charge Qc and the charge Qs mirrored in the semiconductor Qit=|Qc−Qs|, where Qs is calculated for the semiconductor surface barrier VSB measured as a difference between VCPD in the dark and under strong illumination VSB=VCPDDARK−VCPDLIGHT. The flatband voltage, VFB, i.e. the very important parameter that characterizes the interface charge is determined from the value of VCPD when VSB=O. Respective procedures for determining all above parameters are described in details by Lagowski et al. in U.S. Pat. No. 6,037,797, which is herein incorporated by reference.
Since its introduction in the mid 1990's [See corresponding review article “Contactless Surface Charge Semiconductor Characterization” by D. Schroder, Mat. Sci. Engineering B91–92 pp. 196–210 (2002) and article by Edelman et al., “Non-contact C-V Technique for High-k Applications” AIP Conf. Proc. 683. pp 160–165 (2003)], the corona-voltage metrology has been very successful in replacing conventional MOS capacitance-voltage, C-V, technique for characterization of dielectrics on semiconductor substrates. The MOS C-V requires fabrication of the test MOS capacitors that is done on special “monitor wafers” added to the production wafers for the purpose of monitoring dielectric growth or deposition process. Fabrication of capacitors is done after termination of growth or deposition. It adds to testing expenses and produces a delay between termination of dielectric growth or deposition and the availability of testing data. In the case of process failure, a time delay that often extends to many hours or even days can cause a loss of many production wafers processed during the time delay. The corona charge-voltage metrology can reduce this time delay to a wafer transfer and measuring total time of less than 0.5 h. Reduction of delay time and elimination of capacitor fabrication are evident advantages. However, this metrology still requires the use of monitor wafers.
Monitor wafers occupy space in a production line that could be occupied by production wafers. Furthermore, as semiconductor wafers continue to increase in size and become more expensive, using monitor wafers in a fabrication process becomes prohibitively expensive.
The preferable trend is to abolish monitor wafers and to perform monitoring on small 100 μm×100 μm or smaller test sites of product wafers. The product wafer is the actual production wafer that passes through all sequential stages of IC manufacturing process.
Non-contact electrical monitoring has not been done on the test sites because of the lack of suitable metrology. The existing technology can measure sites typically 2 mm to 10 mm in diameter, i.e., the areas 1000 times larger than the area of miniature test sites on product wafers.
The application of charge-voltage data is not limited to monitoring of dielectrics. Charge-voltage data can also be used for deriving important parameters of semiconductor substrates of product wafers. For example, a value of the generation lifetime can be determined by measuring the voltage time decay, after charging (e.g., measured with a semiconductor charged to deep depletion). This is a useful parameter and a sensitive measure of defects in semiconductors. A detailed discussion can be found in “Contactless Surface Charge Semiconductor Characterization” by D. Schroder, Mat. Sci. Engineering B91–92 pp. 196–210 (2002). The voltage decay after charging can be used for deriving the breakdown voltage of semiconductor and the semiconductor dopant concentration. See discussion in Marinsky et al., “Non-Contact Electrical Doping Profiling” by Marinskiy et. al., Characterization and Metrology for ULSI Technology; 2003 Int. Conf. AIP Conf. Proc. 683, pp. 802–806 (2003).